During their execution, applications usually show different behaviors (called "phases"). Each phase is characterized by a certain behavior (e.g., loop, strided memory, potentially parallel) and by a certain set of constraints (e.g., Quality of Service, deadlines). Detecting these phases at run-time allows to reconfigure the underlying architecture in order to meet different goals:

• Performance improvement
• Power consumption optimization

SC-REX (i.e., "SCheduler for REconfigurable devices on linuX") is a scheduler for heterogeneous platforms consisting of reconfigurable processors. It allows applications:

• Execute part of their code on available reconfigurable processors
• Reconfigure each processor based on the characteristics of the code that is going to be executed

The scheduler is in charge of scheduling tasks on the available processors and trigger their reconfiguration based on the run-time information coming from either the hardware or the operating system.

The scheduler has been designed and implemented in the context of the ERA project. This project, financially supported by the European commission under the FP7 program, aims at studying innovative embedded architectures that can be adapted at run-time based on the current needs.

The license is LGPL for the Supervisor and the Run-Time Library. The example of kernel driver is under GPL license.

The main idea behind the design of SC-REX is that a hardware-specific kernel driver exports the reconfigurable processors as files on the filesystem. On Linux, this can be achieved, for example, by using character devices on dev/ or entries on sys/. Then, a hardware-independent supervisor, running in user level, is in charge of handling the set of processors: it collects the requests coming from the applications, it schedules the tasks on the available processors, and it reconfigures the processors based on the desired goal (e.g., energy efficiency or performance).

All reconfigurable processors are characterized by a set of "properties", that can be configured independently. An example of these properties are issue width, cache size, and so on. Each property can be set by writing a proper value into the related file on the filesystem.

The architecture-dependent information are contained in XML files, so that the supervisor code remains architecture-independent.

Check the wiki for more detailed information.

The current reference platform is a Xilinx Virtex6 FPGA board. The supervisor runs on a Linux distribution (i.e., Evelin on a MicroBlaze soft-core CPU). The reconfigurable hardware consists of the ρ-VEX reconfigurable VLIW.

We want to acknowledge all partners of the ERA project, and in particular prof. Roberto Giorgi (University of Siena), prof. Stephan Wong and Roel Seedorf (University of Delft).